IPSI Transactions on Internet Research

Published in: IPSI Transaction on Internet Research Publisher: IPSI Ltd, Belgrade Open Access: CC-BY-NC-ND DOI: 10.58245/ipsi.tir ISSN: 1820 - 4503

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1. About IPSI TIR Journal 1.1 Scope 1.2 Basics 1.3 Journal Ranking 2. Instructions for Authors 2.1 Submitting an Article 2.2 Methodology 2.3 Creativity 2.4 Synergy 2.5 Charges to the Authors 3. Peer Review Policy 3.1 Peer Review Main Pillars 3.2 Reviewers' Responsibilities 3.3 Authors' Responsibilities 3.4 Editors' Responsibilities & Publication Decisions 4. Conflict of Interest 5. Repeated and Multiple Publication 6. Access, Copyright, and Licensing 7. Identifying and Preventing Misconduct 8. Instructions in the Case of Corrections or Retractions 9. Content Originality and Reproduction, Copyright, and Plagiarism 10. Confidentiality Policy July 2018 | Volume 14 | Number 2 | ISSN 1820 - 4503 (Click here for the whole journal download) Guest Editors: Mutlu, O., Ghose, S., and Ausavarungnirun, R. Special issue - "Recent Advances in DRAM and Flash Memory Architectures" Mutlu, O., Ghose, S., and Ausavarungnirun, R. Guest Editor Introduction Lee, D., Kim, Y., Seshadri, V., Liu, J., Subramanian, L., and Mutlu, O. Tiered-Latency DRAM: Enabling Low-Latency Main Memory at Low Cost IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 5-12. Lee, D., Kim, Y., Pekhimenko, G., Khan, S., Seshadri, V., Chang, K., and Mutlu, O. Adaptive-Latency DRAM: Reducing DRAM Latency by Exploiting Timing Margins IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 13-22. Chang, K. K.; Kashyap, A., Hassan, H., Ghose, S., Hsieh, K., Lee, D., Li, T., Pekhimenko, G., Khan, S., and Mutlu, O. Flexible-Latency DRAM: Understanding and Exploiting Latency Variation in Modern DRAM Chips IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 23-31. Chang, K. K.; Yağlıkçı, A. G., Ghose, S., Agrawal, A., Chatterjee, N., Kashyap, A., Lee, D., O’Connor, Mike., Hassan, H., and Mutlu, O. Voltron: Understanding and Exploiting Voltage–Latency–Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Effciency IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 32-40. Hassan, H., Vijaykumar, N., Khan, S., Ghose, S., Chang, K., Pekhimenko, G., Lee, D., Ergin, O., and Mutlu, O. SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 41-52. Seshadri, V., Kim, Y., Fallin, C., Lee, D., Ausavarungnirun, R., Pekhimenko, G., Luo, Y., Mutlu, O., Gibbons, P. B., Kozuch, M. A., and Mowry, T. C. RowClone: Accelerating Data Movement and Initialization Using DRAM IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 53-62. Chang, K. K.; Nair, P. J.; Ghose, S., Lee, D., Qureshi, M. K., and Mutlu, O. LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 63-70. Cai, Y., Luo, Y., Haratsch, E. F., Mai, K., Ghose, S., and Mutlu, O. Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 71-81. Cai, Y., Luo, Y., Ghose, S., Haratsch, E F.; Mai, K., and Mutlu, O. Read Disturb Errors in MLC NAND Flash Memory IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 82-93. Cai, Y., Ghose, S., Luo, Y., Mai, K., Mutlu, O., and Haratsch, E. F. Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming IPSI Transactions on Internet Research, Vol. 14, No. 2, July 2018, pp. 94-8.